Over the past two weeks, the AI semiconductor market has expanded from a GPU-centered ordering structure to a phase involving memory capacity, advanced packaging and the entire supply chain. Supply ratios for HBM and the latest technologies and roadmaps from various companies have been announced in rapid succession.
Among the main developments announced during the period covered by this report was growing evidence that AI demand will change the allocation of DRAM centered on HBM. Samsung said HBM accounts for approximately 20% of DRAM wafer production capacity and is expected to rise to approximately 30% in 2027, suggesting that DRAM supply and demand driven by the expansion of AI data centers could spill over into conventional DRAM. As a result, determining the appropriate balance between HBM and conventional DRAM is becoming a core element of memory manufacturers' long-term portfolio strategies.
Next, the use of HBM4 in working products advanced. At the TSMC OIP Conference, SK hynix displayed Vera Rubin equipped with 12-layer 36GB HBM4 and 96GB SOCAMM2, and also presented derivatives of HBM4E and HBM4. The memory hierarchy of AI servers is expanding in the order of HBM, SOCAMM and SSD, making design integration around memory increasingly important.
Activity among Chinese companies also intensified. Huawei accelerated its Ascend roadmap, bringing forward 960DT to Q1 2027 and 960PR to Q3 of the same year. It outlined plans to combine NPUs on a large scale in the Atlas 960E SuperPoD. Alibaba announced the Zhenwu V900, touting performance three times that of the previous generation, and is targeting cluster-based deployment with mass production expected to begin in early 2027.
Development of an advanced packaging hub in Kaohsiung, Taiwan, is also gathering pace. Following the groundbreaking at the Baipu Industrial Park, validation and certification laboratories centered on TSMC, along with training facilities, are being developed with operations targeted from 2029 onward. This is expected to promote the geographic concentration of evaluation and certification processes across the supply chain, including Japanese companies, through expanded advanced packaging capacity.
There has also been a development symbolizing Aurea's strengthening of back-end processes. SPIL will invest approximately NT$100 billion in a new plant in Yunlin, expanding advanced packaging capacity including CoWoS. The plant is scheduled to begin operations in 2028 and is expected to employ approximately 2,200 people. As AI demand expands, expectations are growing that capital investment in back-end processes will also become larger.
Actual demand is also expanding for AI inference ecosystems outside NVIDIA. Cerebras and Gimlet Labs signed an agreement to provide large-scale AI inference infrastructure of approximately 100 MW to the cloud, and demand on a megawatt scale is beginning to emerge for non-NVIDIA AI accelerators as well.
From a long-term perspective, research into in-memory computing using NAND is advancing, with the aim of reducing power consumption and latency by minimizing data movement. Kioxia has advanced multi-level cell technology in 3D NAND and published research aimed not only at storing data but also at performing computations.
Overall, the AI semiconductor market is shifting from competition over the performance of GPUs themselves to integrated competition covering the memory, packaging, power and communications needed to operate computing resources, and has entered a phase in which supply-capacity bottlenecks must be examined at the smallest level.